UVU v18
| Core | Readiness as catalogued | Role in the product |
|---|---|---|
fir | Source plus testbench | Conditioning and decimating the digitised beat or acoustic signal |
fft | Source plus documentation | Beat frequency into range bins; spectral features for vibration |
cfar | Source plus documentation | Adaptive-threshold detection |
| streaming interconnect | Source only | Back-pressure and instrumentation taps |
| interface bridge | Source plus documentation | To be re-scoped to an industrial fieldbus |
| integration top level | Source plus testbench | End-to-end chain integration |
One of the six is source only. We publish the grading because an inventory that hides its weakest rows is not an inventory.
As of our own engineering audit of May 2026: no core had ever been simulated and none had been synthesised. No constraint files existed anywhere. There is therefore no clock frequency, no logic utilisation, no DSP-block count and no power figure for any core. Five defects are logged. Two datasheet figures were found not to be present in the source, and are being corrected.
This is the reason the verification programme exists, and it is why this site has no specifications page. There are no specifications to state yet.
| Ref | Item | Status |
|---|---|---|
BUG-FIR-1 | Documentation describes a structure the implementation does not match | Marked fixed — unverified |
BUG-FIR-2 | Dead accumulator | Marked fixed — unverified |
BUG-FFT-1 | Illegal declaration inside a case statement — a blocker; the design will not elaborate | Open |
BUG-FFT-2 | Bit-growth sizing; unused parameter | Open |
BUG-CFAR-1 | Leading and lagging sums | Marked fixed — unverified |
DOC-1 | Two datasheet figures not present in the source | Correction in progress |
REPO-1 | Two copies of the integration top level diverge | Resolved in weeks 1–2 |
| Weeks | Dates | Work |
|---|---|---|
| 1–2 | 5 – 18 Oct 2026 | Toolchain, one-command regression, repository consolidation |
| 3–4 | 19 Oct – 1 Nov | Simulate fir against its golden model; close two defects |
| 5–6 | 2 – 15 Nov | Simulate fft; close the elaboration blocker; correct the datasheet |
| 7–8 | 16 – 29 Nov | Simulate cfar; re-parameterise for an industrial clutter profile |
| 9–10 | 30 Nov – 13 Dec | End-to-end chain bench |
| 11–12 | 14 – 27 Dec | Timing constraints; synthesise for an AMD Artix-7 XC7A100T; record frequency, utilisation, DSP-block count and power with tool version and settings stated |
| 13 | 28 Dec – 3 Jan 2027 | Reissue every datasheet, each figure carrying its basis |
| — | by 15 Jan 2027 | Publish |
Every published figure carries its basis: the device and its speed grade, the tool and its version, the settings, and whether timing was met and by what margin. A number without its basis is worse than no number, because it invites a question the company cannot answer and turns a technical conversation into a credibility problem. Until a figure can be published with its basis, it is labelled a design target pending test and evaluation — or it is not published. The golden reference models and the testbenches are available for technical due diligence under a non-disclosure agreement.
Every table and paragraph here is published on the site and can be checked page by page: the core ledger and the May 2026 audit at https://uvu.com.tr/en/signal-processing.html, the defect list, the schedule and the rule for every figure at https://uvu.com.tr/en/verification.html. This document contains no claim that is not on the site. Questions, including sceptical ones: engagement@uvu.com.tr